1. Field of the Invention
The present invention relates to the field of read only memory devices, and more particularly to a ROM (Read-Only-Memory) array with twisted bit lines.
2. Description of the Related Art
In a known manner, a ROM memory cell comprises a single MOS (Metal Oxide Semiconductor) transistor. Owing to this very simple structure, a ROM array can theoretically have a very high level of integration. However, electromagnetic interactions occur between certain bit lines of the ROM array when these lines get too close to one another. A binary value stored in a cell may then be misread by means of a bit line connecting this cell, because of the interactions between this line and other bit lines situated close by. The integration level of a ROM array is therefore limited by the interactions between the bit lines.
Various improvements are already being used for combining a high level of integration of the ROM array with a good read reliability of the stored information.
One of these improvements can be mentioned here which involves the pairing of bit lines within the ROM array. The binary value stored in each cell is then read differentially: the read signal that is detected on the bit line connecting the cell in which the binary value is read is compared with a signal reference level supplied by the bit line that belongs to the same pair as the read bit line. For this purpose, the two bit lines of a same pair are connected to inputs of a differential amplifier disposed at the output of the memory array. Thus, each bit line also serves as internal reference for the memory array during a read operation carried out by means of the bit line with which it is paired. However, such a method only provides a sufficiently reliable read operation if both bit lines of a same pair are disposed in an identical or symmetrical manner within the memory array.
For this purpose, some ROM arrays are divided into two symmetrical portions, and the bit lines of a same pair respectively belong to one and the other of the two portions. Such a ROM array configuration is referred to as ‘open’. The output interface of the array and the read differential amplifiers are then situated between the two portions of the array, so as to be connected at their inputs to the bit lines of each pair respectively output from the two portions of array. However, the connection of the output interface to circuits external to the memory array, for which the values being read are intended, is not straightforward by reason of the space occupied by the two portions of the array on either side of the interface.
A second configuration of a ROM array with differential read mode has been proposed, which does not present the aforementioned size and space issue around the output interface. This second configuration is referred to as ‘folded’. Each of the two portions of array is inserted into the other portion, by alternating the rows of ROM cells of each portion on a common part of substrate. But in this case, the configuration of the word lines respectively associated with the rows of cells, above the surface of the substrate, requires the provision of spacing intervals between the cells. This then results in an increase of 25% in the surface area of the ROM array which limits the level of integration.
In order to avoid this increase in the surface area of the ROM array, a third configuration has been proposed, according to which the bit lines are distributed between two levels of metallization overlaid above the substrate surface. The ROM array is then divided into segments of cell matrix, in the direction of the bit lines. Within each segment, the cells are connected to the bit line situated in the lower metallization level, in other words the metallization level closest to the substrate surface. Between two successive segments of matrix, the bit lines are exchanged between the two levels. Although this third configuration of a ROM array is also of the type with differential read mode, the read operation reliability obtained again becomes insufficient for higher levels of integration. Indeed, it has been observed that, within each matrix segment, a given bit line interacts with another bit line when the two bit lines have respective portions adjacent to one another within the same metallization level. In other words, the read signal detected on one bit line may be altered by the electrical state of some of the other bit lines of the ROM array.
Finally, the document U.S. Pat. No. 6,657,880 describes a static random access memory, or SRAM, array in which the bit lines are displaced between two successive segments of the memory array. These displacements are either parallel to the memory plane, in the direction of the word lines, or perpendicular to the memory plane. A bit line that is displaced perpendicularly to the memory plane is transferred between two different metallization levels. Such a configuration of the bit lines is suitable for an SRAM memory array, where each memory cell comprises six transistors. However, it is not suitable for a ROM array, where each cell is much smaller since it only comprises a single transistor.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.